1. Field of Invention
Exemplary embodiments of the present invention relate to a semiconductor memory device and a method of operating the same and, more particularly, to a semiconductor memory device having a plurality of memory cells coupled to bit lines and a method of operating the same.
2. Description of Related Art
Memory cells are coupled to bit lines, and data are input to or output from the memory cells through the bit lines. In a NAND flash memory device, page buffers sense data from memory cells or store data in the memory cells through bit lines. When 2-bit data consisting of least significant bit (LSB) data and most significant bit (MSB) data are stored in a single memory cell, a page buffer may include two latch circuits composed of a cache latch circuit and a main latch circuit that latch the LSB data and the MSB data, respectively. After a program operation is performed to store data, an operation (e.g., a program verify operation) of checking a status of the stored data is performed.
In order for invalid columns having defective memory cells or unused redundancy memory cells not to affect a status check operation such as a program verify operation, data (e.g., user data) may be input after a default value of the cache latch circuit is set to 1.When LSB data of ‘1’ is inputted, a memory cell is sensed as being in an erase status. Therefore, an invalid column may be sensed as being in a pass status and does not affect the status check operation. In an MSB program operation that stores MSB data, when the MSB data is input as ‘1’, both LSB data and MSB data are ‘1’. A threshold voltage level of a memory cell is determined depending on the LSB data and MSB data. Therefore, the memory cell has a threshold voltage of less than 0 V, that is, an erase status, and the invalid column may be sensed as being in a pass status during a status check operation without being programmed.
However, when the threshold voltage of the defective memory cell among the memory cells is higher than 0 V and does not decrease, the LSB data of the defected memory cell may be sensed as ‘0’. Thus, even when the data is input as ‘1’, a program operation does not change the threshold voltage of the defective memory cell. As a result, a program operation is sensed as being incomplete during the status check operation such as a program verify operation.
For these reasons, there has been a demand for a method of precluding a program operation from being sensed as being a fail status due to defective memory cells during a status check operation.